Repeatedly counting the number of set bits is required in graphics and cryptography operations. Known methods for counting these bits include                checking each bit in turn, keeping a running total of the number of set bits found by incrementing a counter when the checked bit is a ‘1’,        clearing the least significant set bit of the word using x=x & (x−1) where ‘&’ signifies the logical AND operation while keeping a count of the number of times that a set bit has been cleared until the word is all zeros after which the count is returned,        using a lookup table to count bits in part of the word, summing the results from the individual parts and        generating intermediate words by masking and shifting, summing the intermediate words into derivative word fields representing the sum of a group of bits in the word and summing the fields of the derivative word with shift, add and mask operations whereby the resulting sum value represents the number of set bits in the data wordwith the best performing of the above methods using shift operations (see column 1, line 10 through column 2, line 35 of U.S. Pat. No. 6,516,330 B1 “Counting Set Bits in Data Words” to Hicks et al, hereinafter referred to as Hicks). Shifting is also taught in U.S. Pat. No. 4,486,848 “Microprocessor Parallel Additive Execution of a Computer Count Ones Instruction” to Kaminski (see column 1, lines 40-55).        
In addition to Hicks, U.S. Pat. No. 5,717,616 “Computer Hardware Instruction and Method for Computing Population Counts” to Morris and U.S. Pat. No. 5,734,599 “Performing a Population Count Using Multiplication” to Lee et al (hereinafter Lee) also identify counting the number of 1s as useful for many types of algorithms especially cryptographic analysis (see Morris column 1, line 10 through column 3, line 5 and Lee column 1, line 5 through column 2, line 40). Morris further presents the need in the industry for a new apparatus and method that can be implemented conveniently resulting in greater CPU design flexibility and faster computation than prior art methods while Lee suggests the desirability of alternate ways to efficiently perform such calculations with a minimum of hardware. A circuit with a substantially reduced size is also taught as an improvement in U.S. Pat. No. 4,607,176 “Tally Cell Circuit” to Burrows et al (see column 1, line 50 through column 2, line 10).
Though the above approaches identify set bit counting hardware and performance requirements, the expense and complexity of the shifters, multipliers and parallel circuitry in the prior art may provide little if any benefits in transmission or other applications that count the number of unset or zero bits in data characterized by a significantly smaller number of differing values (e.g. either heavily or sparsely populated as in the discussion of the ones density requirement of T1 digital signals in column 1, line 45 through column 2, line 45 of U.S. Pat. No. 5,682,405 “Ones Density Monitor” to Smith: 175+/−75 consecutive zeroes in the definition of carrier loss as well as circuitry for detecting when at least four of thirty-two bits are set to indicate carrier on line status or the lost carrier reset flag).